🔗Team activity between 2018 and 2023

The following text has been written by the ACES team as part of the 2018-2023 periodic HCÉRES evaluation of the LTCI lab and reflects the past activities of the team on the "Embedded Real-Time Systems" topic.

Mixed Criticality Systems (MCS) must manage the uncertain worst-case costs of resources, like execution and energy, under optimistic or pessimistic estimates. High-criticality tasks run regardless of these costs, while low-criticality tasks might be scaled back or dropped in high-criticality mode to free resources for more critical tasks ("Scheduling Multi-Periodic Mixed-Criticality DAGs on Multi-Core Architectures"). Our research includes developing a global static scheduler for MCS that handles task dependencies efficiently on multi-processors ("Scheduling Multi-Periodic Mixed-Criticality DAGs on Multi-Core Architectures", "Generalized Mixed-Criticality Static Scheduling for Periodic Directed Acyclic Graphs on Multi-Core Processors"), and its implementation on the Litmus-RT kernel ("Litmus-RT plugins for global static scheduling of mixed criticality systems"). This work aims to extend the mixed-criticality concept to other resources, enhancing energy efficiency and application to drone swarms and connected devices.

In predictable computing, the focus is on the interplay between critical real-time software and its execution platform to ensure high performance and provable WCET bounds, overcoming hardware design issues that may introduce timing anomalies ("The Role of Causality in a Formal Definition of Timing Anomalies"). Our contributions include a more expressive definition of timing anomalies ("The Role of Causality in a Formal Definition of Timing Anomalies"), an optimal cache model for WCET analysis ("Precise, efficient, and context-sensitive cache analysis"), extensions to the TDM bus arbitration scheme for mixed-criticality systems ("Arbitration-Induced Preemption Delays","Work-conserving dynamic time-division multiplexing for multi-criticality systems"), and a formal framework for modeling DDR memory controllers in Coq ("A formal framework to design and prove trustworthy memory controllers").

Additionally, collaborations with Nanyang Technological University led to a survey on timing-constrained resource allocation techniques in cloud computing ("A survey on time-sensitive resource allocation in the cloud continuum"), and research on detecting instantaneous cycles in component-based simulation models to ensure sound behavioral composition ("Online cycle detection for models with mode-dependent input and output dependencies").